Hackaday

Visualizing Verilog Simulation

You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some ...
Hackaday

FPGAs In C With Cynth

Programming an FPGA with Verilog looks a lot like programming. But it isn’t, at least not in the traditional sense. There have been several systems that aim to take C code and convert it into a ...
EDN

Assertion Methodologies for Verilog Design

Sometimes good ideas take a while to catch on in engineering practice. The use of in-line assertions to document assumptions and check for problems in RTL code is one such idea. Long ago proposed for ...
EDN

‘Obfuscators’ render Verilog, VHDL unreadable

Santa Cruz, Calif. — Providing a new approach to intellectual property (IP) protection, software engineering firm Semantic Designs has released production-quality “obfuscators” for Verilog 2001 and ...
Linux Journal

Open Source in Electronic Design Automation

The world of open-source software is making inroads into areas beyond operating systems, Internet and desktop applications, GUIs and scripting languages. One less well-known area of open-source ...