How atomic-layer deposition and hybrid dielectrics are redefining reliability and scaling for AI-era semiconductors.

Recently, that number has risen to five, and while it adds far more flexibility for structuring electronic equipment, it also brings greater complexity and ratchets up the number of design decisions ...

Over 40% of semiconductor facilities announced since 2021 are located in watersheds projected to face high water stress between 2030 and 2040.

They also would like to use low-leakage transistors to reduce the refresh power demands of large memory arrays. Amorphous oxide semiconductors like IGZO (indium gallium zinc oxide) offer acceptable ...

A new technical paper titled “The Quest for Reliable AI Accelerators: Cross-Layer Evaluation and Design Optimization” was ...

AI squeezes consumer memory market; 3D-IC basics, challenges; atomistic simulation; GPUs and auto security; AI-assisted training.

A new technical paper titled “Scaling of Two-Dimensional Semiconductor Nanoribbons for High-Performance Electronics” was published by researchers at Purdue University, National University of Singapore ...

AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge ...

ALD for Ru wiring; vertical nanolasers; hydrogel semiconductors.

Semiconductor Engineering tracked 12 rounds of $100 million or more in Q4 and 11 in Q3, a significant increase from earlier ...

Beyond cold plates lies what’s sometimes called direct impingement, or direct liquid cooling (DLC), meaning that coolant ...

John Kibarian, CEO of PDF Solutions, talks with Semiconductor Engineering’s Ed Sperling about the growing role of AI in chip ...