IEEE

A 4.2 Gb/S $5^{\text {th }}$ Generation F-Chip of Toggle 5.1 Specification With All-Path Speed Boosting Scheme and Sca Protocol for High Density Nand Flash Applications

Abstract: This paper introduces a $4.2 ~\text{Gb} / \mathrm{s} 5^{\text {th }}$ generation F-chip operating at a 1.1 V supply voltage. To achieve high-speed performance even in high-capacity memory ...
IEEE

A 2.16-pJ/b 112-Gb/s PAM-4 Transceiver With Time-Interleaved 2-b/3-b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28-nm CMOS

Abstract: This article presents a 112-Gb/s four-level pulse amplitude modulation (PAM-4) transceiver (TRX) for extra-short-reach (XSR) applications in 28-nm CMOS. The receiver (RX) adopts a 4 × 6 time ...